This invention is directed to testing memory cell oxides and more particularly to stress testing a memory cell oxide of a dynamic random access memory device otherwise known as a DRAM.
FIG. 1 shows a critical bitline and wordline (X) decoder circuitry of a prior art folded bitline DRAM 10 with an N channel X decoder 20.
In DRAM 10 of FIG. 1, memory blocks 40a, 40b, 40c, and 40d each have two memory cells (i.e., access MOSFETS mc 42a, a'; 42b, b'; 42c, c', and 42d, d', respectively). Each memory cell 42a, a'-d, d' has one capacitor 44a, a'-d, d', respectively. Access MOSFETs mc (42a, a'-d-d') are arranged in a linear sequence (hereinafter called the X direction) to form two bitlines 16a, b of a multi-bitline DRAM 10. If the memory cells are grouped into pairs where alternating wordlines wl0 (No. 18a in FIG. 1), wl2, . . . , wln-2 (18c) connect memory cells 40a-d to a bitline wire 110 designated bt in FIG. 1, and alternating wordlines wll (18b), wl3, . . . , wln-1 (18d) connect memory cells to a bitline wire 112 adjacent to bt and designated as bc in FIG. 1, then bitline wires bt (110) and bc (112) are said to be half bitlines. This adjacency of half bitlines is called a folded bitline architecture and is the preferred arrangement of memory cells in DRAMs in commercial production today. Completing the two bitlines 16a, 16b are precharge devices 30a, b comprising MOSFETs mpt (32a, b), mpc (34a, b) and mp (36a, b), respectively; isolation devices 50a, b comprising isolation MOSFETs mit (52a, b) and mic (54a, b), respectively, which could in some applications be N channel depletion MOSFETs, P channel MOSFETs or even CMOS transmission gates; a sense amplifier 60a, b; and finally; bitline access (Y Select) device 70a, b comprising MOSFETs which could in some applications be CMOS transmission gates or, even P channel MOSFETs.
In DRAM 10, memory cells 40a-d store the data. In order for there to be efficient utilization of silicon area in a memory device, it is advantageous to have as many of these memory cells as possible in each bitline 16a, b. For n memory cells connected to a single bitline, each memory cell is connected to a unique wordline so as to generate a sequence of wordlines designated wl0 (No. 18a in FIG. 1), wl1 (No. 18b in FIG. 1), wl2, . . . , wln-2 (No. 18c in FIG. 1), wln-1 (No. 18d in FIG. 1). Multiple bitlines placed adjacent to one another form a rectangular array of m bitlines designated bitline0 (No. 16a in FIG. 1), bitline1 (not shown), . . . , bitlinem-1 (16b) and connected together by n wordlines and a few control signals such as pblt (taken off pblt node 122), sense (taken off node 129), etc. In a modern DRAM, for each array, typically the number of wordlines n=255, and the number of bitlines is m=1023. The DRAM will have a number of such arrays. For any DRAM, the practical upper limits for n, m, and the number of arrays are then constrained by having a large enough signal to be read by the sense amplifier (constraint on n) and by active power consumption (constraint on m and the number of arrays).
The operation of DRAM 20 shown in FIG. 1 is best explained by reference to FIG. 2 which shows idealized waveforms for DRAM 10. While dummy cells are used on most (but not all) DRAMs to supply a fixed offset to sense amplifier 60a, b, the dummy cells have been omitted here to simplify the figures and discussion. It will be appreciated that the invention may be used on DRAMs with or without dummy cells.
Initially, DRAM array 10 is in the inactive precharge state shown at the left edge of the FIG. 2 waveforms. As shown in FIG. 2, wordlines wl0 (No. 18a in FIG. 1) through wln-2 (No. 18c in FIG. 1) and Y select (Nos. 70a, b in FIG. 1) signals YS0 through Ysm-1 are in their low (GND) state rendering all memory cell access MOSFETS (Nos. 42a, a'-d, d' in FIG. 1) and Y select MOSFETs (Nos. 72a, b and 74a, b in FIG. 1) nonconductive. In FIG. 2, control signals iso (on iso node No. 124, in FIG. 1) and pblt (on pblt node 122) are at VDD. Since signal pblt (on pblt node No. 122 in FIG. 1) is at VDD, all precharge MOSFETS (Nos. 30a, b in FIG. 1) are in their conductive state precharging all half bitlines bt and bc (Nos. 110 and 112, respectively in FIG. 1) to voltage level vbeq (on vbeq node No. 126 in FIG. 1) whose value is approximately VDD/2 as shown in FIG. 2. Additionally shown in FIG. 2, since the iso signal (on iso node No. 124 in FIG. 1) is at VDD all isolation MOSFETs (Nos. 50a, b in FIG. 1) are in their conductive state precharging sense amplifier (Nos. 60a, b in FIG. 1) nodes t and c (Nos. 62a, 64a of sense amplifier 60a, for example, in FIG. 1) to bitline halves bt and bc respectively (Nos. 110, 112 in FIG. 1) and hence to VDD/2. The sense and restore lines 128, 129 of FIG. 1 are separately precharged to VDD/2 by peripheral circuitry not shown in FIG. 1 and hence all sense amplifier MOSFETs are in a nonconductive state.
Information is read from DRAM 10 through a sequence of operations shown in FIG. 2 beginning on the left hand side of the figure. As shown in FIG. 2, signal pblt (on pblt node No. 122 in FIG. 1) switches to the GND state isolating the bitlines of the selected array and their associated sense amplifier nodes t and c (Nos. 62a,c, for example) from precharge signal vbeq (on vbeq node No. 126 in FIG. 1). One of the n wordline decoders (No. 22 in FIG. 1, for example) is enabled to prepare to connect a memory cell to each bitline in the selected array. This is done by supplying an address on the X decoder address bus which is the output from n channel x decoder 20. Through appropriate logical operations, this causes the selected X decoder 22 node a (No. 22a in FIG. 1) to switch to VDD and its node c (No. 22c in FIG. 1) to switch to GND, the latter transition disconnecting the to be activated wordline (wl0 in FIG. 2) (wl0 is shown as 18a in FIG. 1) from the GND node. As node a (Nos. 22a in FIG. 1) rises to VDD, node d (No. 22d in FIG. 1) rises from an intermediate level (shown as VDD-Vtn in FIG. 2) to a voltage that is greater than VDD by at least one N channel threshold voltage (Vtn), thus allowing node b (No. 22b in FIG. 1) to be precharged to VDD. Node d (No. 22d in FIG. 1) is then discharged to VDD or to VDD-Vtn as shown in FIG. 2 rendering MOSFET ma (Nos. 22e in FIG. 1) nonconductive and isolating node b (No. 22b in FIG. 1) at a voltage level of VDD. As there are a number of circuit techniques available to do this in common use in DRAMs a detailed explanation will not be given here.
The memory cell read operation is now initiated by the transition of wordline clock rclk (taken from line No. 29 in FIG. 1) from GND to a boosted or bootstrapped level that is at least Vtn above VDD. Since MOSFET mb (22g in FIG. 1) is in the conductive state wordline Wl0 (No. 18a in FIG. 1) follows rclk taken from rclk node (No. 29 in FIG. 1) from GND to the boosted level. As the rclk signal (on rclk line No. 29 in FIG. 1) and the wl0 signal (on wl0 line No. 18a in FIG. 1) rise, the channel capacitance of MOSFET mb (No. 22g in FIG. 1) increases the voltage of node b (No. 22b in FIG. 1) thus maintaining it in the conductive state. Thus wordline wl0 (No. 18a in FIG. 1) can be fully charged to the final boosted level of rclk (taken from rclk line No. 29 in FIG. 1).
The rise of wordline wl0 (No. 18a in FIG. 1) makes conductive the appropriate memory cell access MOSFETs (mc) (No. 42a, b in FIG. 1) allowing the selected memory cells to discharge to (or be charged from) their respective half bitlines. In FIG. 2, wordline wl0 (No. 18a in FIG. 1) is shown discharging a memory cell to half bitline bt (No. 110 in FIG. 1) thus imparting a slightly greater voltage on half bitline bt relative to bitline bc (No. 112 in FIG. 1) which is not connected to a memory cell. The resulting small voltage difference between half bitlines bt and bc is then propagated through isolation MOSFETs mit (Nos. 52a, b in FIG. 1, respectively) and mic (Nos. 54a, b in FIG. 10) onto sense amplifier nodes t and c (Nos. 62a and 64a in FIG. 1, respectively). This small voltage signal can be amplified by the sense amplifier by switching the sense signal (from sense node 129 in FIG. 1) to GND and the restore signal (from restore node 128 in FIG. 1) to VDD. As the operation of the sense amplifier has been described in detail elsewhere and is common to all DRAMs it will not be described in detail here. The final sense amplifier voltages of node c (64a, b in FIG. 1) at GND and node t (node 62a, b in FIG. 1) at VDD are then propagated back through the isolation MOSFETs onto half bitlines bt and bc (Nos. 110 and 112 in FIG. 1, respectively). In the case of DRAM 10 in FIG. 1, the isolation MOSFETs (Nos. 50a, b in FIG. 1) are N channel MOSFETs and the iso signal (taken from its node No. 124 in FIG. 1) must be boosted to a voltage level at least one Vtn above VDD as shown in FIG. 2 to allow half bitline bt to rise to VDD. Finally, after the sense amplifier (Nos. 60a,b in FIG. 1) has been latched, designated Y select MOSFETs (Nos. 72a, 74a in FIG. 1) may be enabled to read the sense amplifier data to peripheral circuits or to allow new data to be written onto the sense amplifier and bitline nodes.
The DRAM memory array is returned to its inactive state by discharging the wordline wl0 to GND thus isolating the memory cells, returning the appropriate Y select signals to their inactive (GND) state and, then activating the precharge MOSFETs to precharge the bitline and sense amplifier nodes. After a suitable precharge time another cycle may begin.
In order to economically increase the data storage capacity of DRAMs, the physical sizes of the components used to manufacture them has steadily decreased, driven by advances in process technology. The dielectric thicknesses of the oxide layers in the MOSFETs and capacitors used to fabricate modern DRAMs, for example, are now less than 100 angstroms, and, the voltages applied to these MOSFETs generate electric fields that may cause permanent stress damage to the MOSFET gate and memory cell capacitor oxides (Nos. 44a, a'-d, d' in FIG. 1). Wordline access MOSFET mc (Nos. 42a, a'-d, d' in FIG. 1) and isolation MOSFETs mit and mic (Nos. 52a,b, 54a,b in FIG. 1) of DRAM 10 in FIG. 1 are particularly vulnerable because wordlines and the iso signal (taken from node 124 in FIG. 1) are driven to extraordinarily high boosted voltages while node bt or bc (Nos. 110, 112 in FIG. 1, respectively) is driven to GND.
In order to guarantee the long term reliability of semiconductor components including DRAMs these products are prestressed by operating the products for a brief period of time (usually 24 hours) at voltages and temperatures in excess of those permitted in normal operation. The object of the applied stress is to induce the failure of units that may have microscopic production defects while in this so called "burn in" environment. Failed units can be discarded prior to shipment to the end use customer. The effects of a given voltage and/or temperature overstress for a given unit of time are very well understood in the semiconductor industry. It is thus possible to use these overstress techniques to accurately predict failure rates of most semiconductor components including DRAMs.
Performing burn in on DRAMs, however, is substantially more difficult than for general CMOS logic circuits such as NAND gates, INVERTERs, etc. In part, this is because MOSFET mc (Nos. 42a, a-d, d' in FIG. 1), and isolation MOSFETs mit and mic (Nos. 52a,b, 54a,b in FIG. 1) are already driven to abnormally high voltages while other nodes, such as the memory cell reference node vplate 130, is driven to an abnormally low voltage. The oxide of the memory cell capacitors cc (Nos. 44a, a'-dd, d') in FIG. 1) also has its own specific burn in requirements. These requirements have become increasingly difficult to perform without the application of damaging overvoltages to wordline and isolation circuitry of the DRAM and, possibly even to general purpose CMOS logic circuits peripheral to the DRAM.